This invention relates to protection circuits at the input and output pads of integrated circuits (IC), especially for complementary metal-oxide-semiconductor (CMOS) IC.
Electrostatic Discharge (ESD) is a serious problem in IC design. Due to electrostatic potential buildup in a human body, the static voltage as high as thousands of volts can appear at the input and output bonding pads of an IC and cause catastrophic failures by excessive current through the output device or the power supply. For reliability, the IC must be designed to protect against such ESD.
For the protection at input pads, the high ESD voltage can be clamped by a Zener diode through a high resistance. However, such a scheme is not useful for the output pads, because the high resistance would drop the output voltage.
For the protection at the output pads, any ESD voltage must be clamped to a low voltage without any series resistance. Recently, the silicon controlled rectifier (SCR) with a pnpn structure has been proposed for protection at the output pad, as described by A. Chatterjee and T. Polgreen in a paper, "A Low-Voltage Triggering SCR for On-Chip ESD Protection at Output and Input Pads", IEEE Electron Device Letters, Vol.12, No.1, January 1991, pp.21-22. The low on voltage of an SCR is utilized to clamp the output pads. This prior art is known as a "LVTSCR" protection circuit and is shown in FIG. 1. The basic structure is an n-well CMOS IC. The output device to be protected is an n-channel metal-oxide-semiconductor transistor (NMOS) pull-down device with a lightly-doped drain (LDD) structure. The LDD structure is widely used to reduce the undesirable "short-channel effect". This NMOS has a source 12 connected to ground and a drain 10 connected the output pad 11. Low-doped diffusions 16 and 18 are placed next the the drain 10 and source 12 respectively. The ESD protection is furnished by the SCR structure 80 shown in the left-hand side of FIG. 1. The SCR comprises an n-well 78 and an LDD NMOS 82 with an n+ source 70 and an n+ drain 72 butted against the n-well 78. Inside the n-well is a butted p+diffusion 74 and an n+diffusion 76, which are connected to the output pad 11. The pnpn structure for the SCR is formed by the p+ diffusion 74, n-well 78, p-substrate 80 and n+diffusion 70. An SCR is equivalent to a pnp transistor and an npn transistr connected in a feedback loop. In FIG. 1, the equivalent npn transistor has the n+ diffusion 72 as collector, p-substrate 80 as base and n+diffusion 70 as emitter. The equivalent pnp transistor has p-substrate 80 as collector, the n-well 78 as base and the p+diffusion 74 as emitter. To trigger the SCR from off condition to the low voltage on condition, at least one of the equivalent transistors must be sufficiently turned on with a current to cause the closed loop current gain of the equivalent pnp-npn feedback circuit equal to unity. One method to sufficiently turn on the equivalent npn transistor is to utilize the avalanche breakdown voltage of the n+p- collecotr junction (72/80). When a voltage exceeding the breakdown voltage appears at the I/O pad 11, a large base current flows into the equivalent npn transistor to turn on the SCR. In this LVTSCR protection circuit, the NMOS 82 has the same LDD structure as the output pull-down NMOS 15. For effective protection, the avalanche breakdown voltage of the NMOS 82 in the LVTSCR circuit must be lower than that of the output pull-down NMOS 15. Otherwise the output pull-down NMOS 15 may suffer from thermal runaway. For this reason, the channel length of the triggering NMOS 82 must be shorter than that of the pull-down NMOS 15. However, when the channel is too short, short-circuit may occur. Therefore, the manufacturing torlerance is very small.